This invention relates to MOS transistors and more specifically to vertical current flow MOSFETS.
FIG. 1a illustrates a vertical MOSFET 10 constructed in accordance with the prior art. MOSFET 10 includes an N+ source region 12, a P- body region 14 electrically coupled to source region 12, and an N+ drain region 16. Between P- body region 14 and N+ drain region 16 is an N- region 18 which enhances the junction breakdown voltage between the N+ drain 16 and P- body region 14. (The breakdown voltage of a PN junction between a P- region such as region 14 and an N- region such as region 18 is greater than the breakdown voltage of a junction between a P- region and an N+ region.)
A trench 19 is etched through regions 12, 14, and 18. A layer of gate insulation 20 lines the interior of trench 19 and a polysilicon gate 22 is formed on the gate insulation. When a positive voltage is applied to gate 22 relative to source region 12, transistor 10 turns on, thereby permitting current to flow between drain 16 and source 12, but when zero volts is applied to gate 22 relative to source 12, transistor 10 turns off.
When gate 22 is held at zero volts relative to source 12 and a large voltage is applied to drain 16 relative to source 12, the junction between P- region 14 and N- region 18 is reverse biased. If a sufficiently large voltage is applied to N+ drain 16, the depletion region which normally forms between regions 14 and 18 extends into N+ region 16. When that happens, because of the difference in voltage applied to gate 22 and N+ drain 16, an electric field is generated which causes the junction breakdown voltage between P- body region 14 and N+ drain 16 to decrease. The decrease in breakdown voltage of transistor 10 caused by the above-mentioned electric field is known as premature field-induced breakdown, and is an undesirable phenomenon. (Premature field-induced breakdown is discussed by Wu-Shiung Feng et al. in "MOSFET Drain Breakdown Voltage," published in IEEE Electron Device Letters, Vol. EDL-7, No. 7, July 1986, page 449-450, incorporated herein by reference.)
FIG. 1b illustrates a second transistor 24 constructed in accordance with the prior art. In FIG. 1b, trench 19 only extends partway through N- region 18. Thus, if the depletion region which normally forms between P- region 14 and N- region 18 extends to N+ region 16, the point where the depletion region reaches N+ region 16 is a greater distance from gate 22 than it would be in prior art transistor 10 of FIG. 1a. Thus, the strength of the electric field generated by the voltage applied to gate 22 would be attenuated, and the tendency of transistor 24 to exhibit premature field induced breakdown would be less than that of transistor 10. Unfortunately, in transistor 24, current flowing from drain 16 to source 12 must flow through a region indicated by arrows 26 and 28 which is N- material, and thus adds to the source drain series resistance exhibited by transistor 24. This extra series resistance represents a major disadvantage to transistor 24.
For transistors 10 and 24, the breakdown voltage of the transistor is increased by increasing the thickness of gate insulation 20. Unfortunately, increasing the thickness of insulation 20 increases the transistor threshold voltage and transistor on-resistance--an undesirable result.